1. Field of the Invention
The present invention relates to a nonvolatile memory apparatus, a memory controller, and a memory system having an error correction function each.
2. Description of the Related Art
The nonvolatile memory is a memory which may be accessed in units of data called a page made up of a plurality of bytes or words and which retains data therein after power is removed. Thanks to these features, the nonvolatile memory is used extensively in storage systems accessed in units of a sector. The NAND flash memory is a representative nonvolatile memory (NVM).
In recent years, development and commercialization have been made progress in nonvolatile random access memories (NVRAM's) which are randomly accessible in units of a byte or a word as with the SRAM, DRAM, and other volatile random access memories (RAM's) but which can retain data even after power is turned off. The FeRAM (ferroelectric random access memory), PCRAM (phase change random access memory, and ReRAM (resistance random access memory) are typical NVRAM's.
The NVM uses an error correction code (ECC) to improve data reliability. A high-speed ECC scheme is needed to minimize adverse effects on access speed. One such ECC scheme is an extended Hamming code capable of one-bit error correction and two-bit error detection.
The NVRAM is required to provide random access performance as rapid as that of DRAM's in units of a byte or a word. For this reason, the ECC for the NVRAM needs to constitute a system that permits very rapid error correction in units of a small access unit.
Meanwhile, the higher the ability to correct errors, the longer it takes the ECC scheme to handle error detection and correction and the larger the code size involved. To preserve ECCs along with data in the NVM or NVRAM requires setting aside a redundant bit area in addition to data retention areas in the memory. To use an ECC scheme with a higher error correction capability thus entails appropriating the redundant bit area of a larger capacity than before.
Japanese Patent Laid-open No. 2008-192054 discloses a memory system furnished with an error correction function.
The semiconductor memory system disclosed in the cited patent application utilizes a first error correction code as well as a second error correction code that has a higher correction capability than the first error correction code. If an error correctable by the first error correction code is detected from read data, any error that may occur thereafter is corrected using the second error correction code in order to enhance data reliability.